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?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 no v ember 2010 FOD8012 high cmr, bi-directional, logic gate optocoupler features full duple x, bi-directional 20kv/? minim um common mode rejection high speed: ? 15mbit/sec data rate (nrz) ? 15ns max. pulse width distortion ? 30ns max. propagation delay skew 3.3v and 5v cmos compatibility extended industr ial temper ate r ange , -40 to +110?c temper ature r ange saf ety and regulator y appro v als ? ul1577, 3750 vac rms for 1 min. ? din en/iec60747-5-2 (approval pending) applications industr ial ?ldb us comm unications ? devicenet, can, rs485, rs232 microprocessor system interf ace ? spi, i 2 c prog r ammab le logic control isolated data acquisition system v oltage le v el t r anslator description the FOD8012 is a full duplex, bi-directional, high-speed logic gate optocoupler, which supports isolated commu- nications allowing digital signals to communicate between systems without conducting ground loops or ic design to achieve minimum 20kv/? common mode noise rejection (cmr) rating. this high-speed logic gate optocoupler is highly inte- grated with 2 optically coupled channels arranged in bi-directional configuration, and housed in a compact 8-pin small outline package. each optocoupler channel consists of a high-speed algaas led driven by a cmos buffer ic coupled to a cmos detector ic. the detector ic comprises of an integrated photodiode, a high-speed trans-impedance amplifier and a voltage comparator with an output driver. the cmos technology coupled to the high efficiency of the led achieves low power con- sumption as well as very high speed (60ns propagation delay, 15ns pulse width distortion). related resources fod8001, high noise imm unity , 3.3v/5v logic gate optocoupler datasheet www .f airchildsemi.com/products/opto/ functional sc hematic 1 2 3 45 0.1? bypass capacitor required from v dd to gnd 6 7 8 v dd1 v oa v dd2 v ina v inb gnd 1 v ob gnd 2 t ruth t a b l e vin led v o high off high lo w o n low hazardous voltages. it utilizes fairchild? proprietary co - pla nar packaging technology, optoplanar ? 60ns max. propagation delay , and opti - FOD8012 ?high cmr, bi-directional, logic gate optocoupler
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 2 FOD8012 ?high cmr, bi-directional, logic gate optocoupler pin definitions absolute maximum ratings (t a =25? unless otherwise specified) stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended operating conditions the recommended operating conditions table de?es the conditions for actual device operation. recommended operating conditions are speci?d to ensure optimal performance to the datasheet speci?ations. fairchild does not recommend exceeding them or designing to absolute maximum ratings. pin number pin name description 1v dd1 supply voltage to channel-a detector ic and channel-b buffer ic 2v oa output voltage from channel-a detector ic 3v inb input voltage to channel-b buffer ic 4 gnd 1 ground for channel-a detector ic and channel-b buffer ic 5 gnd 2 ground for channel-a buffer ic and channel-b detector ic 6v ob output voltage from channel-b detector ic 7v ina input voltage to channel-a buffer ic 8v dd2 supply voltage to channel-a buffer ic and channel-b detector ic symbol parameter value units t stg storage temperature -40 to +125 ? t opr operating temperature -40 to +110 ? t j j unction temperature -40 to +130 ? t sol lead solder temperature (refer to re?w temperature pro?e) 260 for 10sec ? v dd1 , v dd2 supply voltage 0 to 6.0 v v ia , v ib input voltage -0.5 to vdd+0.5 v i ia , i ib input dc current -10 to +10 ? v oa , v ob output voltage -0.5 to vdd+0.5 v i oa , i ob av erage output current 10 ma pd i input power dissipation (1) 60 mw pd o output power dissipation (1) 60 mw symbol parameter min. max. unit t a ambient operating temperature -40 +110 ? v dd1 , v dd2 supply voltages (3.3v operation) (2) 3.0 3.6 v supply voltages (5.0v operation) (2) 4.5 5.5 v v ih logic high input voltage 2.0 v dd v v il logic low input voltage 0 0.8 v t r , t f input signal rise and fall time 1.0 ms
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 3 FOD8012 ?high cmr, bi-directional, logic gate optocoupler isolation characteristics apply over all recommended conditions, typical value is measured at t a = 25? electrical characteristics t a = -40? to +110?, 3.0v v dd 5.5v, unless otherwise specified. apply over all recommended conditions, typical value is measured at v dd1 = v dd2 = +3.3v, t a = 25? symbol parameter conditions min. typ. max. units v iso input-output isolation voltage freq = 60hz, t = 1.0min, i i-o 10? (3)(4) 3750 vac rms r iso isolation resistance v i-o = 500v (3) 10 11 ? c iso isolation capacitance v i-o = 0v, freq = 1.0mhz (3) 0.2 pf symbol parameter conditions min. typ. max. units i dd1l , i dd2l logic low supply current v ia , v ib = 0v 5.8 8.0 ma i dd1h , i dd2h logic high supply current v ia , v ib = v dd 2.5 4.0 ma i ia , i ib input current -10 +10 ? v oh logic high output voltage i o = ?0?, v dd = 3.3v, v i = v ih 3.2 3.3 v i o = ?ma, v dd = 3.3v, v i = v ih 3.0 3.1 v i o = ?0?, v dd = 5v, v i = v ih 4.9 5.0 v i o = ?ma, v dd = 5v, v i = v ih 4.7 4.8 v v ol logic low output voltage i o = 20?, v dd = 3.3v or 5v, v i = v il 0 0.1 v i o = 4ma, v dd = 3.3v or 5v, v i = v il 0.26 0.6 v
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 4 FOD8012 ?high cmr, bi-directional, logic gate optocoupler switching characteristics t a = -40? to +110?, 3.0v v dd 5.5v, unless otherwise specified. apply over all recommended conditions, typical value is measured at v dd1 = v dd2 = +3.3v, t a =25? notes: 1. no derating required. 2. 0.1? bypass capacitor must be connected between pin 1 and 4, and 5 and 8. the capacitors should be kept close to the supply pins. 3. device is considered a two terminal device: pins 1, 2, 3 and 4 are shorted together and pins 5, 6, 7 and 8 are shorted together. 4. 3,750 vac rms for 1 minute duration is equivalent to 4,500 vac rms for 1 second duration. 5. pwd is equal to the magnitude of the worst case difference in t phl and/or t plh that will be seen for one channel switching, while holding the other channel output at a low or high state, or while both channels are in synchronous data transmission mode. 6. t psk(cc) is equal to the magnitude of the worst case difference in t phl and/or t plh that will be seen between the two channels within a single device. 7. t psk(pp) is equal to the magnitude of the worst case difference in t phl and/or t plh that will be seen between any two units from the same manufacturing date code that are operated at same case temperature, at same operating conditions, with equal loads. 8. common mode transient immunity at output high is the maximum tolerable positive dvcm/dt on the leading edge of the common mode impulse signal, vcm, to assure that the output will remain high. common mode transient immunity at output low is the maximum tolerable negative dvcm/dt on the trailing edge of the common pulse signal, vcm, to assure that the output will remain low. symbol parameter conditions min. typ. max. units data rate 15 mbit/s t phl propagation delay time to logic low output pw = 66.7ns, c l = 15pf 37 60 ns t plh propagation delay time to logic high output pw = 66.7ns, c l = 15pf 40 60 ns pwd pulse width distortion, | t phl ?t plh | pw = 66.7ns, c l = 15pf (5) 315ns t psk(cc) channel-channel skew pw = 66.7ns, c l = 15pf (6) 12 25 ns t psk(pp) pa r t-part skew pw = 66.7ns, c l = 15pf (7) 30 ns t r output rise time (10% to 90%) pw = 66.7ns, c l = 15pf 6.5 ns t f output fall time (90% to 10%) pw = 66.7ns, c l = 15pf 6.5 ns |cm h | common mode transient immunity at output high v i = v dd1 , v o > 0.8v dd1 , v cm = 1000v (8) 20 40 kv/? |cm l | common mode transient immunity at output low v i = 0v, v o < 0.8v, v cm = 1000v (8) 20 40 kv/?
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 5 FOD8012 ?high cmr, bi-directional, logic gate optocoupler typical performance curves fig. 1 typical output voltage vs. input voltage (channel a & b) v i ? input voltage (v) 012 3 45 4.0 3.0 2.0 1.0 0 3.0 3.5 4.0 4.5 5.0 5.5 2.0 1.8 1.6 1.4 1.2 1.0 v o ? output voltage (v) v dd1 = v dd1 = 3.3v fig. 2 typical input voltage switching threshold vs. input supply voltage (channel a & b) v dd ? supply voltage (v) v ith input voltage switching threshold (v) fig. 3 typical propagation delay vs. ambient temperature (channel a & b) t a ? ambient temperature (?) -40 -20 0 20 40 60 80 100 110 54 50 46 42 38 34 30 t p ?propagation delay (ns) frequency = 7.5mhz duty cycle = 50% v dd1 = v dd2 = 3.3v t plh t phl fig. 4 typical t phl ?t plh vs. ambient temperature (channel a & b) t a ? ambient temperature (?) -40 -20 0 20 40 60 80 100 110 2 1 0 -1 -2 -3 -4 -5 -6 t phl ?t plh (ns) frequency = 7.5mhz duty cycle = 50% v dd1 = v dd2 = 3.3v fig. 5 typical rise time vs. ambient temperature (channel a & b) fig. 6 typical fall time vs. ambient temperature (channel a & b) t a ? ambient temperature (?) -40 -20 0 20 40 60 80 100 110 7.0 6.5 6.0 5.5 5.0 4.5 4.0 t r ?rise time (ns) frequency = 7.5mhz duty cycle = 50% v dd1 = v dd2 = 3.3v t r t f t a ? ambient temperature (?) -40 -20 0 20 40 60 80 100 110 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 t f ?fall time (ns) frequency = 7.5mhz duty cycle = 50% v dd1 = v dd2 = 3.3v
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 6 FOD8012 ?high cmr, bi-directional, logic gate optocoupler typical performance curves (continued) fig. 7 typical propagation delay vs. output load capacitance (channel a & b) c l ? output load capacitance (pf) 15 20 25 30 35 40 45 50 55 45 43 41 39 37 35 t p ?propagation delay (ns) frequency = 7.5mhz duty cycle = 50% v dd1 = v dd2 = 3.3v t plh t phl fig. 8 typical t phl ?t plh vs. output load capacitance (channel a & b) c l ? output load capacitance (pf) 15 20 25 30 35 40 45 50 55 0 -1 -2 -3 -4 -5 t phl ?t plh (ns) t r ?rise time (ns) frequency = 7.5mhz duty cycle = 50% v dd1 = v dd2 = 3.3v fig. 9 typical rise time vs. output load capacitance (channel a & b) c l ? output load capacitance (pf) 15 20 25 30 35 40 45 50 55 12 10 8 6 4 2 frequency = 7.5mhz duty cycle = 50% v dd1 = v dd2 = 3.3v t f ?fall time (ns) fig. 10 typical fall time vs. output load capacitance (channel a & b) c l ? output load capacitance (pf) 15 20 25 30 35 40 45 50 55 16 14 12 10 8 6 4 frequency = 7.5mhz duty cycle = 50% v dd1 = v dd2 = 3.3v t r t f
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 7 FOD8012 ?high cmr, bi-directional, logic gate optocoupler typical performance curves (continued) i dd1 / i dd2 ?input supply current (ma) fig. 11a typical i dd1 /i dd2 supply current vs. frequency f ? frequency (khz) 0 2,000 4,000 6,000 8,000 10,000 12,000 14,000 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 v dd1 = v dd2 = 5.5v, t a = 25? v ina and v inb switching pin 2 and 6 floating t a = 25? t a = -40? t a = 110? i dd1 / i dd2 ?input supply current (ma) fig. 11b typical i dd1 /i dd2 supply current vs. frequency f ? frequency (khz) 0 2,000 4,000 6,000 8,000 10,000 12,000 14,000 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 v dd1 = v dd2 = 5.5v, t a = 25? v inb = 0v @ i dd1 , v ina switching v ina = 0v @ i dd2 , v inb switching pin 2 and 6 floating t a = 25? t a = -40? t a = 110? i dd1 / i dd2 ?input supply current (ma) fig. 11c typical i dd1 /i dd2 supply current vs. frequency f ? frequency (khz) 0 2,000 4,000 6,000 8,000 10,000 12,000 14,000 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 v dd1 = v dd2 = 5.5v, t a = 25? v ina = 0v @ i dd1 , v inb switching v inb = 0v @ i dd2 , v ina switching pin 2 and 6 floating t a = 25? t a = -40? t a = 110?
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 8 FOD8012 ?high cmr, bi-directional, logic gate optocoupler t est circuits figure 11. test circuit for propogation delay time and rise time, fall time figure 12. test circuit for instantaneous common mode rejection voltage v in t plh t r v out v ol 50% 90% 10% input output 3.3v 50% v oh t f t phl 1 2 3 4 5 6 7 8 v dd2 v dd1 v ob v oa 0v~3.3v 0.1 f 0.1 f c l 1 2 3 4 5 6 7 8 v dd2 v dd1 v oa 0.1 f a b 0.1 f c l vcm pulse gen + v ol v cm cm h cm l v oh gnd 0.8 x v dd switching pos. (a), v in = 3.3v switching pos. (b), v in = 0v 0.8v
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 9 FOD8012 ?high cmr, bi-directional, logic gate optocoupler small outline package dimensions note: all dimensions are in millimeters. pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ 0.024 (0.61) 0.050 (1.27) 0.155 (3.94) 0.275 (6.99) 0.060 (1.52) lead coplanarity : 0.004 (0.10) max 0.202 (5.13) 0.182 (4.63) 0.021 (0.53) 0.011 (0.28) 0.050 (1.27) typ 0.244 (6.19) 0.224 (5.69) 0.143 (3.63) 0.123 (3.13) 0.008 (0.20) 0.003 (0.08) 0.010 (0.25) 0.006 (0.16) seating plane 0.164 (4.16) 0.144 (3.66)
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 10 FOD8012 ?high cmr, bi-directional, logic gate optocoupler carrier tape specification note: all dimensions are in millimeters. ordering information all packages are lead free per jedec: j-std-020b standard. marking information option order entry identi?r description no suf? FOD8012 small outline 8-pin, shipped in tubes (50 units per tube) r2 FOD8012r2 small outline 8-pin, tape and reel (2,500 units per reel) 4.0 0.10 1.5 min user direction of feed 2.0 0.05 1.75 0.10 5.5 0.05 12.0 0.3 8.0 0.10 0.30 max 8.3 0.10 3.50 0.20 0.1 max 6.40 0.20 5.20 0.20 1.5 0.1/-0 1 2 5 3 4 de?itions 1 f airchild logo 2 device number 3 one digit year code, e.g., ? 4 tw o digit work week ranging from ?1 to ?3 5 assembly package code 8012 s1 yy x
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 11 FOD8012 ?high cmr, bi-directional, logic gate optocoupler re?w pro?e pro?e freature pb-free assembly pro?e t emperature min. (tsmin) 150? t emperature max. (tsmax) 200? time (t s ) from (tsmin to tsmax) 60?20 seconds ramp-up rate (t l to t p ) 3?/second max. liquidous temperature (t l ) 217? time (t l ) maintained above (t l ) 60?50 seconds p eak body package temperature 245? +0? / ?? time (t p ) within 5? of 245? 30 seconds ramp-down rate (t p to t l ) 6?/second max. time 25? to peak temperature 8 minutes max. te mperature (?) 260 240 220 200 180 160 140 120 100 80 60 40 20 0 t l t s t l t p t p 245 ts m a x ts m i n 120 max. ramp-up rate = 3?/s max. ramp-down rate = 6?/s 240 360 ti me (seconds) t ime 25? to peak
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8012 rev. 1.0.5 12 tradem arks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global subsidiaries ,andisnot intended to be an exhaustive list of all such trademarks. accupower auto-spm build it now coreplus corepower crossvolt ctl current transfer logic deuxpeed dual cool ecospark efficientmax esbc fairchild fairchild semiconductor fact quiet series fact fast fastvcore fetbench flashwriter * fps f-pfs frfet global power resource sm green fps green fps e-series g max gto intellimax isoplanar megabuck microcoupler microfet micropak micropak2 millerdrive motionmax motion-spm optohit optologic optoplanar pdp spm power-spm powertrench powerxs programmable active droop qfet qs quiet series rapidconfigure saving our world, 1mw/w/kw at a time signalwise smartmax smart start spm stealth superfet supersot -3 supersot -6 supersot -8 supremos syncfet sync-lock * the power franchise tinyboost tinybuck tinycalc tinylogic tinyopto tinypower tinypwm tinywire trifault detect truecurrent * " serdes uhc ultra frfet unifet vcx visualmax xs * trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild? worldwide terms and conditions, specifically the warranty therein, which covers the se products. life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. anti-c ounterfeiting policy fairchild semiconductor corporation's anti-counterfeiting policy. fairchild's anti-counterfeiting policy is also stated on our external websi te, www.fairchildsemi.com, under sales support. counterfeiting of semiconductor parts is a growing problem in the industry. all manufacturers of semiconductor products are experiencing counterf eiting of their parts. customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance ,failed applications, and increased cost of production and manufacturing delays. fairchild is taking strong measures to protect ourselves and our customer sfromthe proliferation of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts either directly from fairchild or from au thoriz ed fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or from authorized fairchil dd i stributors are genuine parts, have full traceability, meet fairchild's quality standards for handling and storage and provide access to fairchild's full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and will appropriately address any warranty is sues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unauthorized sources. fairchild is committed to combat th is global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. product status definitions definition of terms datasheet identification product status definition advance information formative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product that is discontinued by fairchild semiconductor. the datasheet is for reference information only. rev. i49 n FOD8012 ?high cmr, bi-directional, logic gate optocoupler

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